The present invention relates to a leak current compensating device and leak current compensating method for a semiconductor device.
Various circuits have an output transistor switched between the ON or OFF state. Patent documents 1 and 2 describe a prior art constant voltage source circuit comprising the output transistor switched between the ON or OFF state. FIG. 5 is a diagram of the prior art constant voltage source circuit. FIG. 5 shows an operational amplifier 1, a reference voltage source 2 outputting a voltage VA, an output transistor 3 as PMOS transistor, an output terminal 4, a power source terminal 5 receiving a source voltage VDD, an NMOS transistor 6, a control terminal 7, and resistance elements 8, 9 and 16.
The operational amplifier 1 is connected to the reference voltage source 2 at inverting input terminal thereof and is connected to the gate of the PMOS transistor 3 at output terminal thereof. The source of the PMOS transistor 3 is connected to the power source terminal 5 and the drain of the PMOS transistor 3 is connected to the output terminal 4 and the resistance elements 8 and 16. The drain of the PMOS transistor 3 is grounded via a series circuit of the resistance elements 8 and 9. The node between the resistance elements 8 and 9 is connected to a noninverting input terminal of the operational amplifier 1. The drain voltage of the PMOS transistor 3 is divided by the resistance elements 8 and 9, and the divided voltage is applied to the noninverting input terminal of the operational amplifier 1.
The control terminal 7 is connected to the gate of the NMOS transistor 6 and a control terminal of the operational amplifier 1. The source of the NMOS transistor 6 is grounded and the drain of the NMOS transistor 6 is connected to the drain of the PMOS transistor 3 via the resistance element 16. Resistance values of the resistance element 8, 9 and 16 are referred to as R1, R2 and R3, respectively.
With the above-mentioned constitution, when a CONT signal (control signal) input to the control terminal 7 is at low level, the operational amplifier 1 goes into the operating (ON) state and the NMOS transistor 6 goes into the OFF state. Controlled by the operational amplifier 1, the PMOS transistor 3 outputs a voltage V=VA (1+R1/R2) from the output terminal 4.
When the CONT signal is at high level, the operational amplifier 1 goes into the non-operating (OFF) state and maintains the state in which the gate voltage of the PMOS transistor 3 is raised to VDD. The PMOS transistor 3 goes into the cut-off (OFF) state. At this time, since the CONT signal is at high level, the NMOS transistor 6 goes into the ON state and passes a current from the output terminal 4 through the resistance element 16. This makes the voltage V of the output terminal 4 to be ground potential.
As described above, the prior art constant voltage source circuit controls the voltage of the output terminal 4 in accordance with the CONT signal. In the case of normal operation (the CONT signal is at low level), the output terminal 4 outputs the voltage V=VA (1+R1/R2). In the case of output shutdown (the CONT signal is at high level), the voltage V of the output terminal 4 becomes ground potential (V=0).